Automatic Ga Based Evolution of Fault Tolerant Digital Circuits

Genetic Algorithm based automatic evolution of fault tolerant digital circuits has been examined at three different levels. At the first level, multiple working designs are automatically generated, offline, without additional human design effort and each is documented with the unused resources information. This information is used for fault tolerance. Depending on the number of versions generated, up to 100% single component fault coverage can be achieved. The second level examines the effect of providing additional resources by increasing the dimensionality of the evolved circuit. Finally, the addition of a fault tolerant layer that has been examined guarantees simultaneous single component fault coverage. All these techniques have been tested for gate level, functional level and Configurable Logic Block (CLB) level evolution and the results have been analyzed. The techniques have been tested for simple combinatorial circuits and an ISCAS ’89-benchmark circuit.